Drain Bias Stress-Induced Degradation in Amorphous Silicon Thin Film Transistors with Negative Gate Bias

In this study, degradation of amorphous silicon thin film transistors (a-Si TFTs) under drain bias (V-d) stresses with fixed negative gate bias (V-g) has been investigated. For DC Vd stress, state creation mechanism dominates the threshold voltage (V-th) degradation for relative large negative V-gd (V-g-V-d) while state creation and/or electron trapping dominates for positive Vgd. For AC V-d stress, state creation, electron trapping and hole trapping contribute to the degradation. Dominant mechanism depends on stress time, frequency and the polarity of V-gd. Decreasing stress voltage suppresses state creation and/or hole trapping for -V-gd condition, but enhances state creation and/or electron trapping for +V-gd condition.