Generic carrier-based core model for undoped four-terminal double-gate MOSFETs valid for symmetric, asymmetric, and independent-gate-operation modes

被引：32

作者：

Liu, Feng ^{[1
]}

He, Jin ^{[1
,3
]}

Fu, Yue ^{[2
]}

Hu, Jinhua ^{[1
]}

Bian, Wei ^{[2
]}

Song, Yan ^{[2
]}

Zhang, Xing ^{[1
,3
]}

Chan, Mansun ^{[4
]}

机构：

[1] Peking Univ, Sch Elect Engn & Comp Sci, Inst Microelect, Multiproject Wafer Ctr, Beijing 100871, Peoples R China

[2] Peking Univ, Dept Microelect, Grp Nano & Tera Devices & Circuits, Beijing 100871, Peoples R China

[3] Peking Univ, Shenzhen Grad Sch, Sch Comp & Informat Engn, Shenzhen 518055, Peoples R China

[4] Hong Kong Univ Sci & Technol, Dept Elect & Comp Sci, Kowloon, Hong Kong, Peoples R China

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2008年 / 55卷 / 03期

关键词：

carrier-based model; circuit simulation and design; compact modeling; double-gate (DG) MOSFET; nonclassical device;

D O I：

10.1109/TED.2007.914836

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A generic carrier-based core model for undoped four-terminal double-gate (DG) MOSFETs has been developed and is presented in this paper. The model is valid for symmetric, asymmetric, and independent-gate-operation modes. Based on the exact) solution of the 1-D Poisson's equation in a general DG MOSFET configuration, a rigorous derivation of the drain-current equations from the Pao-Sah's double integral has been performed. By using the channel carriers as the intermediate variable, a very compact analytical drain-current expression can be obtained. The model is extensively verified by comparisons with a 2-D numerical simulator under a large number of biasing conditions. The concise mathematical formulation allows the unification of various DG models into a carrier-based core model for a compact DG MOSFET model development.

引用

页码：816 / 826

页数：11

共 28 条

[1]

*BSIM MOD, BERK SHORT CHANN IGF

[2] Novel gate concepts for MOS devices [J].

Colinge, JP .

ESSDERC 2004: PROCEEDINGS OF THE 34TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2004, :45-49

[3] A process/physics-based compact model for nonclassical CMOS device and circuit design [J].

Fossum, JG ;

Ge, L ;

Chiang, MH ;

Trivedi, VP ;

Chowdhury, MM ;

Mathew, L ;

Workman, GO ;

Nguyen, BY .

SOLID-STATE ELECTRONICS, 2004, 48 (06) :919-926

[4]

FOSSUM JG, 2006, P 2006 NSTI NAN C WO, P674

[5] Device scaling limits of Si MOSFETs and their application dependencies [J].

Frank, DJ ;

Dennard, RH ;

Nowak, E ;

Solomon, PM ;

Taur, Y ;

Wong, HSP .

PROCEEDINGS OF THE IEEE, 2001, 89 (03) :259-288

[6]

He J, 2006, SEMICOND SCI TECH, V21, P261, DOI 10.1088/0268-1242/21/3/008

[7]

He J, 2004, NSTI NANOTECH 2004, VOL 2, TECHNICAL PROCEEDINGS, P124

[8]

He J, 2007, IEEE T ELECTRON DEV, V54, P1203, DOI [10.1109/TED.2007.893812, 10.1109/IED.2007.893812]

[9] A carrier-based analytic DCIV model for long channel undoped cylindrical surrounding-gate MOSFETs [J].

He, Jin ;

Zhang, Xing ;

Zhang, Ganggang ;

Chan, Mansun ;

Wang, Yangyuan .

SOLID-STATE ELECTRONICS, 2006, 50 (03) :416-421

[10] Double-gate CMOS: Symmetrical-versus asymmetrical-gate devices [J].

Kim, K ;

Fossum, JG .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2001, 48 (02) :294-299

← 1 2 3 →