A Hardware-Oriented Echo State Network for FPGA Implementation

This paper proposes implementation of an echo state network (ESN) to field programmable gate array FPGA). The proposed method is able to reduce hardware resources by using fixed-point operation, quantization of weights, which includes accumulate operations and efficient dataflow modules. The performance of the designed circuit is verified via experiments including prediction of sine and cosine waves. Experimental result shows that the proposed circuit supports to 200[MHz] of operation frequency and facilitates faster computing of the ESN algorithm compared with a central processing unit.