Floating-point fused multiply-add architectures

被引：0
|
作者：
Quinnell, Eric [1 ]
Swartzlander, Earl E., Jr.
Lemonds, Carl
机构：
[1] Univ Texas Austin, AMD, Austin, TX 78712 USA
来源：
CONFERENCE RECORD OF THE FORTY-FIRST ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS & COMPUTERS, VOLS 1-5 | 2007年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Two new floating-point fused multiply-add architectures for the single instruction execution of (A x B) + C are presented. The three-path architecture uses parallel hardware paths similar to those in dual-path floating-point adders. The new bridge architecture re-uses common floating-point components to add a fused multiply-add instruction. Each new architecture as well as 2 collection of floating-point arithmetic units and a classic fused multiplier-adder have been designed using the Advanced Micro Devices 65 nanometer silicon on insulator CMOS technology to fairly compare the new architectures.
引用
收藏
页码：331 / +
页数：2
相关论文
共 50 条
  • [1] Fused Multiply-Add for Variable Precision Floating-Point
    Nannarelli, Alberto
    32ND IEEE INTERNATIONAL SYSTEM ON CHIP CONFERENCE (IEEE SOCC 2019), 2019, : 342 - 347
  • [2] Floating-point fused multiply-add with reduced latency
    Lang, T
    Bruguera, JD
    ICCD'2002: IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS, 2002, : 145 - 150
  • [3] Bridge Floating-Point Fused Multiply-Add Design
    Quinnell, Eric
    Swartzlander, Earl E., Jr.
    Lemonds, Carl
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2008, 16 (12) : 1726 - 1730
  • [4] Floating-point fused multiply-add: Reduced latency for floating-point addition
    Bruguera, JD
    Lang, T
    17TH IEEE SYMPOSIUM ON COMPUTER ARITHMETIC, PROCEEDINGS, 2005, : 42 - 51
  • [5] Multiple path IEEE floating-point fused multiply-add
    Seidel, PM
    PROCEEDINGS OF THE 46TH IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS & SYSTEMS, VOLS 1-3, 2003, : 1359 - 1362
  • [6] Floating-Point Fused Multiply-Add under HUB Format
    Hormigo, Javier
    Villalba-Moreno, Julio
    Gonzalez-Navarro, Sonia
    2020 IEEE 27TH SYMPOSIUM ON COMPUTER ARITHMETIC (ARITH), 2020, : 1 - 8
  • [7] Decimal floating-point fused multiply-add with redundant internal encodings
    Han, Liu
    Zhang, Hao
    Ko, Seok-Bum
    IET COMPUTERS AND DIGITAL TECHNIQUES, 2016, 10 (04): : 147 - 156
  • [8] An efficient multiple precision floating-point Multiply-Add Fused unit
    Manolopoulos, K.
    Reisis, D.
    Chouliaras, V. A.
    MICROELECTRONICS JOURNAL, 2016, 49 : 10 - 18
  • [9] Proxy Bits for Low Cost Floating-Point Fused Multiply-Add Unit
    Kim, Hyunpil
    Moon, Sangook
    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2016, 25 (10)
  • [10] Development of a RISC-V-conform fused multiply-add floating-point unit
    Kaiser F.
    Kosnac S.
    Brüning U.
    Supercomputing Frontiers and Innovations, 2019, 6 (02) : 64 - 74
12345