A Novel Dry Selective Etch of SiGe for the Enablement of High Performance Logic Stacked Gate-All-Around NanoSheet Devices

被引:63
作者
Loubet, N. [1 ]
Kal, S. [2 ]
Alix, C. [2 ]
Pancharatnam, S. [1 ]
Zhou, H. [1 ]
Durfee, C. [1 ]
Belyansky, M. [1 ]
Haller, N. [1 ]
Watanabe, K. [1 ]
Devarajan, T. [1 ]
Zhang, J. [1 ]
Miao, X. [1 ]
Sankar, M. [1 ]
Breton, M. [1 ]
Chao, R. [1 ]
Greene, A. [1 ]
Yu, L. [1 ]
Frougier, J. [1 ]
Chanemougame, D. [2 ]
Tapily, K. [2 ]
Smith, J. [2 ]
Basker, V. [1 ]
Mosden, A. [2 ]
Biolsi, P. [2 ]
Hurd, T. Q. [2 ]
Divakaruni, R. [1 ]
Haran, B. [1 ]
Bu, H. [1 ]
机构
[1] IBM Res, Albany, NY 12203 USA
[2] TEL Technol Ctr, Albany, NY USA
来源
2019 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2019年
关键词
D O I
10.1109/iedm19573.2019.8993615
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, we demonstrate a first of a kind SiGe dry etch technique for the formation of inner spacers and for channel release, enabling stacked NanoSheet (NS) gate-all-around device architectures. This novel etch involves a precisely controlled lateral SiGe etch with very high selectivity to Si. A detailed characterization of this novel process and its selectivity and tunability as a function of Ge concentration are discussed. The outstanding 150:1 selectivity for SiGe25% versus Si of this process makes it the best candidate for inner spacer shape and depth control, and enables a wide range of NS device widths on the same wafer with low Si channel thickness variability, which is critical for power/performance optimization of high performance computing stacked NS devices. As a result, very low transistor threshold voltage and subthreshold slope variations versus device width are measured. The reduced Si channel (sheet) thinning obtained with this etch process improves device performance over the standard etch method, as measured by drain current, max transconductance and bias-temperature instability.
引用
收藏
页数:4
相关论文
共 10 条
  • [1] Bae G, 2018, INT EL DEVICES MEET
  • [2] Impact of tunnel etching process on electrical performances of SON devices
    Caubet, V
    Borel, S
    Arvet, C
    Bilde, J
    Chanemougame, D
    Monfray, S
    Ranica, R
    Mazoyer, P
    Skotnicki, T
    [J]. JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2005, 44 (7B): : 5795 - 5798
  • [3] Lauer I., 2015, S VLSI TECH, pT140
  • [4] Loubet N, 2017, S VLSI TECH, pT230, DOI 10.23919/VLSIT.2017.7998183
  • [5] Loubet N., 2018, ECS MEET ABSTR MA201, P1075, DOI DOI 10.1149/MA2018-02/31/1075
  • [6] Selective etching of Si1-xGex versus Si with gaseous HCl for the formation of advanced CMOS devices
    Loubet, Nicolas
    Kormann, Thomas
    Chabanne, Guillaume
    Denorme, Stephane
    Dutartre, Didier
    [J]. THIN SOLID FILMS, 2008, 517 (01) : 93 - 97
  • [7] Mertens H, 2016, INT EL DEVICES MEET
  • [8] Mocuta A, 2018, 2018 IEEE SYMPOSIUM ON VLSI TECHNOLOGY, P147, DOI 10.1109/VLSIT.2018.8510683
  • [9] Nonlinear Unmixing of Hyperspectral Data via Deep Autoencoder Networks
    Wang, Mou
    Zhao, Min
    Chen, Jie
    Rahardja, Susanto
    [J]. IEEE GEOSCIENCE AND REMOTE SENSING LETTERS, 2019, 16 (09) : 1467 - 1471
  • [10] Yeung CW, 2018, INT EL DEVICES MEET