This paper presents a new linearizing circuit, which gives high power-added efficiency with low distortion for the W-CDMA application. Since this linearizing circuit is realized by adding a small transistor, a resistor and a capacitor to the bias circuit, the required chip size is small enough and no extra loss in the signal path occurs. The designed 1.95 GHz two-stage power amplifier using HBTs shows 44% power-added-efficiency (PAE), 27.6 dBm output power and 21 dB gain with -37 dBc adjacent channel leakage power ratio (ACLR), at a supply voltage of 3.4 V. In contrast, the conventional power amplifier without linearizer shows 3 dB degradation in ACLR under the same conditions described above. Also, the chip size, which directly affects cost, is less than 1 mm(2).