Three-layer laminated metal gate electrodes with tunable work functions for CMOS applications

被引:31
作者
Bai, WP
Bae, SH
Wen, HC
Mathew, S
Bera, LK
Balasubramanian, N
Yamada, N
Li, MF
Kwong, DL
机构
[1] Univ Texas, Microelect Res Ctr, Dept Elect & Comp Engn, Austin, TX 78758 USA
[2] Inst Microelect, Singapore, Singapore
[3] Anelva Corp, Fuchu, Tokyo 1838508, Japan
[4] Natl Univ Singapore, Dept Elect & Comp Engn, Silicon Nano Device Lab, Singapore 117548, Singapore
关键词
CMOS; laminated metal gate; metal gate; metal nitride; work function;
D O I
10.1109/LED.2005.844701
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This letter presents a novel technique for tuning the work function of a metal gate electrode. Laminated metal gate electrodes consisting of three ultrathin (similar to 1-nm) layers, with metal nitrides (HfN, TiN, or TaN) as the bottom and top layers and element metals (Hf, Ti, or Ta) as the middle layer, were sequentially deposited on SiO2, followed by rapid thermal annealing annealing. Annealing of the laminated metal gate stacks at high temperatures (800 degrees C-1000 degrees C) drastically increased their work functions (as much as 1 eV for HfN-Ti-TaN at 1000 degrees C). On the contrary, the bulk metal gate electrodes (HfN, TiN and TaN) exhibited consistent midgap work functions with only slight variation under identical annealing conditions. The work function change of the laminated metal electrodes is attributed to the crystallization and the grain boundary effect of the laminated structures after annealing. This change is stable and not affected by subsequent high-temperature process. The three-layer laminated metal gate technique provides PMOS-compatible work functions and excellent thermal stability even after annealing at 1000 degrees C.
引用
收藏
页码:231 / 233
页数:3
相关论文
共 14 条
[1]   Impact of gate workfunction on device performance at the 50 nm technology node [J].
De, I ;
Johri, D ;
Srivastava, A ;
Osburn, CM .
SOLID-STATE ELECTRONICS, 2000, 44 (06) :1077-1080
[2]  
HAUSER JR, 1997, CRITICAL FRONT MAT P
[3]   Work function of binary alloys [J].
Ishii, R ;
Matsumura, K ;
Sakai, A ;
Sakata, T .
APPLIED SURFACE SCIENCE, 2001, 169 :658-661
[4]  
Lee J, 2002, INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST, P359, DOI 10.1109/IEDM.2002.1175852
[5]   Dual-metal gate technology for deep-submicron CMOS transistors [J].
Lu, Q ;
Yee, YC ;
Ranade, P ;
Takeuchi, H ;
King, TJ ;
Hu, CM ;
Song, SC ;
Luan, HF ;
Kwong, DL .
2000 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2000, :72-73
[6]  
MAYER JW, 1990, ELECT MAT SCI, P170
[7]   WORK FUNCTION OF ELEMENTS AND ITS PERIODICITY [J].
MICHAELSON, HB .
JOURNAL OF APPLIED PHYSICS, 1977, 48 (11) :4729-4733
[8]   Dual work function metal gate CMOS transistors by Ni-Ti interdiffusion [J].
Polishchuk, I ;
Ranade, P ;
King, TJ ;
Hu, CM .
IEEE ELECTRON DEVICE LETTERS, 2002, 23 (04) :200-202
[9]   Dual work function metal gate CMOS technology using metal interdiffusion [J].
Polishchuk, I ;
Ranade, P ;
King, TJ ;
Hu, CM .
IEEE ELECTRON DEVICE LETTERS, 2001, 22 (09) :444-446
[10]  
Ranade P, 2002, INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST, P363, DOI 10.1109/IEDM.2002.1175853