Co-Design of a High Performance 12-bit 8GHz DDR4 Switch on a Laminate-based CSP (Chip Scale Packaging) Technology

被引：1

作者：

Li, Ming ^{[1
]}

Moreira-Tamayo, Oscar ^{[1
]}

Murugan, Rajen ^{[1
]}

机构：

[1] Texas Instruments Inc, 13020 TI Blvd,MS 3621, Dallas, TX 75243 USA

来源：

2016 IEEE 66TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC) | 2016年

关键词：

DDR4; CSP; nFBGA; Co-Design; High-Speed;

D O I：

10.1109/ECTC.2016.221

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Multiplexer/switch ICs are key components of NVDIMM architecture that serve to isolate the host controller from the DRAM memory system. Signal integrity performance of the IC can drastically be impacted by package parasitics. In this paper we detailed a system co-design methodology that was employed to design a cost-effective DDR4 switch packaged in a laminate-based chip-scale packaging (CSP), without compromising electrical performance. The co-design simulation methodology is validated through correlation to laboratory measurements on TI's TS3DDR4000 (TM) - a high performance 12-bit 8GHz DDR4 switch.

引用

页码：992 / 996

页数：5

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