A 5.8 GHz linear power amplifier in a standard 90nm CMOS process using a 1V power supply

被引:26
作者
Haldi, Peter [1 ]
Chowdhury, Debopriyo [1 ]
Liu, Gang [1 ]
Niknejad, Ali M. [1 ]
机构
[1] Univ Calif Berkeley, Dept EECS, Berkeley Wireless Res Ctr, Berkeley, CA 94704 USA
来源
2007 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS (RFIC) SYMPOSIUM, DIGEST OF PAPERS | 2007年
关键词
power amplifiers; CMOS power amplifier; power combiners;
D O I
10.1109/RFIC.2007.380917
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A fully integrated 5.8 GHz Class AB linear power amplifier (PA) in a standard 90nm CMOS process using thin oxide transistors utilizes a novel on-chip transformer power combining network. The transformer combines the power of four push-pull stages with low insertion loss over the bandwidth of interest and is compatible with standard CMOS process without any additional analog or RF enhancements. With a 1 V power supply, the PA achieves 24.3dBm maximum output power at a peak drain efficiency of 27% and 20.5dBm output power at the I dB compression point.
引用
收藏
页码:431 / +
页数:2
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