Pre-Bond Probing of TSVs in 3D Stacked ICs

Through-Silicon Via (TSV)-based 3D stacked ICs (SICs) are becoming increasingly important in the semiconductor industry, yet pre-bond testing of TSVs continues to be difficult with current technologies. In this paper, we present a test and DFT method for pre-bond testing of TSVs using probe technology. We describe the on-die test architecture and probe technique needed for TSV testing, in which individual probe needles make contact with multiple TSVs at a time. We also describe methods for capacitance and resistance measurements, as well as stuck-at and leakage tests. Simulation results using HSPICE are presented for a TSV network. We demonstrate that we can achieve high resolution in these measurements, and therefore high accuracy in defect detection when we target one or multiple TSVs at a time. We also show that the test outcome is reliable even in the presence of process variations or multiple defective TSVs.