Reducing power consumption in FPGA routing

被引：0

作者：

Zamani, MS ^{[1
]}

Esmaili, E ^{[1
]}

机构：

[1] Amirkabir Univ Technol, Dept Comp Engn, Tehran, Iran

来源：

CCECE 2003: CANADIAN CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING, VOLS 1-3, PROCEEDINGS: TOWARD A CARING AND HUMANE TECHNOLOGY | 2003年

关键词：

FPGA; routing; power;

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

One of the major drawbacks of field programmable gate arrays is their poor energy efficiency. This paper focuses on the routing phase of FPGA design and attempts to optimize dynamic power consumption in FPGA interconnect. Power optimization is performed with small side effects on circuit performance and area. Our enhancements to the VPR Timing Driven algorithm reduced the FPGA routing power by about 10% with negligible loss in circuit performance.

引用

页码：9 / 12

页数：4