A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology

被引：136

作者：

Devarajan, Siddharth ^{[1
]}

Singer, Larry ^{[1
]}

Kelly, Dan ^{[1
]}

Pan, Tao ^{[1
]}

Silva, Jose ^{[1
]}

Brunsilius, Janet ^{[2
]}

Rey-Losada, Daniel ^{[2
]}

Murden, Frank ^{[3
]}

Speir, Carroll ^{[3
]}

Bray, Jeffery ^{[2
]}

Otte, Eric ^{[1
]}

Rakuljic, Nevena ^{[2
]}

Brown, Phil ^{[3
]}

Weigandt, Todd ^{[2
]}

Yu, Qicheng ^{[1
]}

Paterson, Donald ^{[1
]}

Petersen, Corey ^{[2
]}

Gealow, Jeffrey ^{[1
]}

Manganaro, Gabriele ^{[1
]}

机构：

[1] Analog Devices Inc, Wilmington, MA 01887 USA

[2] Analog Devices Inc, San Diego, CA 92128 USA

[3] Analog Devices Inc, Greensboro, NC 27409 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2017年 / 52卷 / 12期

关键词：

Calibration; CMOS; digitally assisted analog design; direct RF sampling analog-to-digital converter (ADC); gigahertz data conversion; interleaved (IL) ADC; pipeline ADC; switched capacitor; A/D CONVERTER; GHZ; MHZ; DB; 10-BIT;

D O I：

10.1109/JSSC.2017.2747758

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 12-bit 10-GS/s interleaved (IL) pipeline analog-to-digital converter (ADC) is described in this paper. The ADC achieves a signal to noise and distortion ratio (SNDR) of 55 dB and a spurious free dynamic range (SFDR) of 66 dB with a 4-GHz input signal, is fabricated in the 28-nm CMOS technology, and dissipates 2.9 W. Eight pipeline sub-ADCs are interleaved to achieve 10-GS/s sample rate, and mismatches between sub-ADCs are calibrated in the background. The pipeline sub-ADCs employ a variety of techniques to lower power, like avoiding a dedicated sample-and-hold amplifier (SHA-less), residue scaling, flash background calibration, dithering and inter-stage gain error background calibration. A push-pull input buffer optimized for high-frequency linearity drives the interleaved sub-ADCs to enable >7-GHz bandwidth. A fast turn-ON bootstrapped switch enables 100-ps sampling. The ADC also includes the ability to randomize the sub-ADC selection pattern to further reduce residual interleaving spurs.

引用

页码：3204 / 3218

页数：15

共 35 条

[1] A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter [J].