Reliability study of organic complementary logic inverters using constant voltage stress

被引：3

作者：

Wrachie, N. ^{[1
]}

Cester, A. ^{[1
]}

Lago, N. ^{[1
]}

Rizzo, A. ^{[1
]}

D'Alpaos, R. ^{[2
]}

Stefani, A. ^{[2
]}

Turatti, G. ^{[2
]}

Muccini, M. ^{[2
,3
]}

Meneghesso, G. ^{[1
]}

机构：

[1] Univ Padua, Dept Informat Engn, I-35131 Padua, Italy

[2] ETC Srl, I-40129 Bologna, Italy

[3] CNR ISMN Bologna, I-40129 Bologna, Italy

来源：

SOLID-STATE ELECTRONICS | 2015年 / 113卷

关键词：

Organic Thin-Film Transistors; Reliability; Bias stress; Logic inverter; THIN-FILM TRANSISTORS; SEMICONDUCTORS; TRANSPORT; MOBILITY; EXPOSURE; TFTS;

D O I：

10.1016/j.sse.2015.05.028

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We performed constant voltage stresses with different bias conditions on all-organic complementary inverters. We found a 20% maximum variation of DC inverter parameters after a 10(4)-s stress. However, the largest stress-induced degradation was found in the delay times, which increased by a factor as high as 7. This is mainly due to the threshold voltage variation of the p-type thin-film-transistor and the mobility reduction of the n-type thin-film transistors, which both decrease the saturation drain current. (C) 2015 Elsevier Ltd. All rights reserved.

引用

页码：151 / 156

页数：6

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