HPPC 2010: Forth Workshop on Highly Parallel Processing on a Chip

被引：0
|
作者：
Forsell, Martti [1 ]
Traff, Jesper Larsson [2 ]
机构：
[1] VTT Tech Res Ctr Finland, Oulu, Finland
[2] Univ Vienna, Dept Comp Sci, Fac Comp Sci, Vienna, Austria
来源：
EURO-PAR 2010 PARALLEL PROCESSING WORKSHOPS | 2011年 / 6586卷
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
引用
收藏
页码：73 / 75
页数：3
相关论文
共 50 条
  • [1] HPPC 2010: Forth workshop on highly parallel processing on a chip
    Forsell, Martti
    Träff, Jesper Larsson
    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 2011, 6586 LNCS : 73 - 75
  • [2] HPPC 2010: 5th Workshop on Highly Parallel Processing on a Chip
    Forsell, Martti
    Traff, Jesper Larsson
    EURO-PAR 2011: PARALLEL PROCESSING WORKSHOPS, PT I, 2012, 7155 : 245 - 247
  • [3] HPPC 2007:: Workshop on highly parallel processing on a chip -: Foreword
    Forsell, Martti
    Traff, Jesper Larsson
    EURO-PAR 2007 WORKSHOPS: PARALLEL PROCESSING, 2008, 4854 : 3 - 4
  • [4] Second workshop on highly parallel processing on a chip (HPPC 2008)
    Forsell, Martti
    Träff, Jesper Larsson
    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 2009, 5415 LNCS : 123 - 125
  • [5] HPPC 2009: 3rd Workshop on Highly Parallel Processing on a Chip
    Forsell, Martti
    Traeff, Jesper Larsson
    EURO-PAR 2009 PARALLEL PROCESSING WORKSHOPS, 2010, 6043 : 3 - +
  • [6] CONFIGURABLE, HIGHLY PARALLEL (CHIP) APPROACH FOR SIGNAL-PROCESSING APPLICATIONS
    SNYDER, L
    PROCEEDINGS OF THE SOCIETY OF PHOTO-OPTICAL INSTRUMENTATION ENGINEERS, 1982, 341 : 8 - 16
  • [7] CHIP ARCHITECTURES FOR PARALLEL PROCESSING
    DETTMER, R
    ELECTRONICS AND POWER, 1985, 31 (03): : 227 - 231
  • [8] Parallel processing in the isoelectric focusing chip
    Zilberstein, GV
    Baskin, EM
    Bukshpan, S
    ELECTROPHORESIS, 2003, 24 (21) : 3735 - 3744
  • [9] Development of three-dimensional integration technology for highly parallel image-processing chip
    Lee, Kang Wook
    Nakamura, Tomonori
    Sakuma, Katsuyuki
    Park, Ki Tae
    Shimazutsu, Hiroaki
    Miyakawa, Nobuaki
    Kim, Ki Yoon
    Kurino, Hiroyuki
    Koyanagi, Mitsumasa
    Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, 2000, 39 (5 B): : 2473 - 2477
  • [10] Development of three-dimensional integration technology for highly parallel image-processing chip
    Lee, KW
    Nakamura, T
    Sakuma, K
    Park, KT
    Shimazutsu, H
    Miyakawa, N
    Kim, KY
    Kurino, H
    Koyanagi, M
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 2000, 39 (4B): : 2473 - 2477
12345