Comparative Study of Approximate Multipliers

被引：24

作者：

Masadeh, Mahmoud ^{[1
]}

Hasan, Osman ^{[1
]}

Tahar, Sofiene ^{[1
]}

机构：

[1] Concordia Univ, Dept Elect & Comp Engn, Montreal, PQ, Canada

来源：

PROCEEDINGS OF THE 2018 GREAT LAKES SYMPOSIUM ON VLSI (GLSVLSI'18) | 2018年

关键词：

Approximate Computing; Approximate Multiplier; Power-efficiency;

D O I：

10.1145/3194554.3194626

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Approximate multipliers are widely being advocated for energy-efficient computing in applications that exhibit an inherent tolerance to inaccuracy. In this paper, we identify three decisions for design and evaluation of approximate multiplier circuits: (1) the type of approximate full adder (FA) used to construct the multiplier, (2) the architecture, i.e., array or tree, of the multiplier and (3) the placement of sub-modules of approximate and exact multipliers in the target multiplier module. Based on FA cells implemented at the transistor level (TSMC65nm), we developed several approximate building blocks of 8x8 multipliers, as well as various implementations of higher order multipliers. These designs are evaluated based on their power, area, delay and error and the best designs are identified. We validate these designs on an image blending application using MATLAB, and compare them to related work.

引用

页码：415 / 418

页数：4

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