Fast algorithms for slew-constrained minimum cost buffering

被引:40
作者
Hu, Shiyan [1 ]
Alpert, Charles J.
Hu, Jiang
Karandikar, Shrirang K.
Li, Zhuo
Shi, Weiping
Sze, C. N.
机构
[1] Texas A&M Univ, Dept Elect & Comp Engn, College Stn, TX 77843 USA
[2] IBM Austin Res Lab, Austin, TX 78758 USA
关键词
Index Terms-Buffer insertion; input slew; interconnect; NP-complete; slew constraint;
D O I
10.1109/TCAD.2007.906477
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
As a prevalent constraint, sharp slew rate is often required in circuit design, which causes a huge demand for buffering resources. This problem requires ultrafast buffering techniques to handle large volume of nets while also minimizing buffering cost. This problem is intensively studied in this paper. First, a highly efficient algorithm based on dynamic programming is proposed to optimally solve slew buffering with discrete buffer locations. Second, a new algorithm using the maximum matching technique is developed to handle the difficult cases in which no assumption is made on buffer input slew. Third, an adaptive buffer selection approach is proposed to efficiently handle slew buffering with continuous buffer locations. Fourth, buffer blockage avoidance is handled, which makes the algorithms ready for practical use. Experiments on industrial netlists demonstrate that our algorithms are very effective and highly efficient: we achieve about 90 x speedup and save up to 20 % buffer area over the commonly used van Ginneken style buffering. The new algorithms also significantly outperform previous works that indirectly address the slew buffering problem.
引用
收藏
页码:2009 / 2022
页数:14
相关论文
共 19 条
[11]   An O(bn2) time algorithm for optimal buffer insertion with b buffer types [J].
Li, Z ;
Shi, WP .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2006, 25 (03) :484-489
[12]   Optimal wire sizing and buffer insertion for low power and a generalized delay model [J].
Lillis, J ;
Cheng, CK ;
Lin, TTY .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1996, 31 (03) :437-447
[13]   Spec-based repeater insertion and wire sizing for on-chip interconnect [J].
Menezes, N ;
Chen, CP .
TWELFTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 1999, :476-482
[14]  
OSLER PJ, 2004, P ACM INT S PHYS DES, P190
[15]   Repeater scaling and its impact on CAD [J].
Saxena, P ;
Menezes, N ;
Cocchini, P ;
Kirkpatrick, DA .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2004, 23 (04) :451-463
[16]   A fast algorithm for optimal buffer insertion [J].
Shi, WP ;
Li, Z .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2005, 24 (06) :879-891
[17]  
Shi WP, 2004, ASIA S PACIF DES AUT, P609
[18]  
VANGINNEKEN LPPP, 1990, 1990 IEEE INTERNATIONAL SYMP ON CIRCUITS AND SYSTEMS, VOLS 1-4, P865, DOI 10.1109/ISCAS.1990.112223
[19]  
WESTE NH, 1993, PRINCIPLES CMOS VLSI, P221