Impact of the Current Density Increase on Reliability in Scaled BJT-selected PCM for High-Density Applications

被引：12

作者：

Redaelli, A. ^{[1
]}

Pirovano, A. ^{[1
]}

Tortorelli, I. ^{[1
]}

Ottogalli, F. ^{[1
]}

Ghetti, A. ^{[1
]}

Laurin, L. ^{[1
]}

Benvenuti, A. ^{[1
]}

机构：

[1] Numonyx, R&D Technol Dev, I-20041 Agrate Brianza, Italy

来源：

2010 INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM | 2010年

关键词：

Phase Change Memory; Reliability; BJT selector; PCM endurance; heater degradation;

D O I：

10.1109/IRPS.2010.5488760

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Some of the largest semiconductor companies involved in the non volatile memory business have demonstrated that Phase-Change Memory (PCM) technology has today reached the product maturity at 90 and 65 nm nodes and 45 nm platform is under development. In this approaches the architectural choice for large density arrays decoding relies on silicon diodes or BJT-selected PCMs (BJT-PCM), thus defining it as the mainstream PCM non-volatile memory technology. However to continue the PCM technology scaling roadmap the current density required to program the storage element will increase linearly with the lithography reduction, becoming of the order of tens of MA/cm(2) in the BJT selector and of hundreds of MA/cm(2) in the storage element at ultra-scaled lithographic nodes. In the ITRS 2008 the maximum current density to program a PCM cell has been recognized as the main physical mechanism that can impact the reliability of scaled PCM devices and it can be a serious show-stopper for this technology beyond the 32 nm technology node. Aim of this paper is to investigate the impact of the increasing current density on the functionality and reliability of scaled BJT-PCM architecture down to the 16 nm node

引用

页码：615 / 619

页数：5

共 8 条

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[2]

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