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A New Fault-Tolerant MLI-Investigating Its Skipped Level Performance
被引:16
作者:
Prasadarao, V. S. K.
[1
]
Peddapati, Sankar
[2
]
Naresh, S. V. K.
[2
]
机构:
[1] Shri Vishnu Engn Coll Women, Dept Elect & Elect Engn, Bhimavaram 534202, India
[2] Natl Inst Technol Andhra Pradesh, Tadepalligudem 534101, India
关键词:
Topology;
Switches;
Circuit faults;
Fault tolerant systems;
Fault tolerance;
Inverters;
Through-silicon vias;
Skipped voltage level;
fault-tolerant structure;
multilevel inverter (MLI);
pulsewidth modulation (PWM);
renewable energy sources;
5-LEVEL INVERTER TOPOLOGY;
MULTILEVEL INVERTER;
VOLTAGE;
SINGLE;
CONVERTER;
9-LEVEL;
D O I:
10.1109/TIE.2021.3062259
中图分类号:
TP [自动化技术、计算机技术];
学科分类号:
0812 ;
摘要:
Generating higher voltage levels with fewer power electronic components and fault tolerance is a challenging issue for multilevel inverters (MLIs). In this article, a new generalized fault tolerant MLI (FTMLI) with reduced semiconductor switches is presented. The proposed FTMLI topology contains more redundant switching states; thus, the topology can tolerate faults in both switches and/or sources. This article also introduces the new level shifted carrier pulsewidth modulation technique in effective utilization of abnormal voltage level combinations (or skipped voltage level) for running emergency loads. The proposed topology's operation is discussed along with the fault-tolerant capability for both the symmetric and asymmetric modes. Experimental results are presented to show the effectiveness of the FTMLI topology using the associated control strategy. A comparative analysis between the proposed topology and other MLI topologies is also provided to highlight the proposed topology's merits.
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页码:1432 / 1442
页数:11
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