A low power charge-recycling CMOS clock buffer

被引：5

作者：

Wang, XH ^{[1
]}

Porod, W ^{[1
]}

机构：

[1] Univ Notre Dame, Dept Elect Engn, Notre Dame, IN 46556 USA

来源：

NINTH GREAT LAKES SYMPOSIUM ON VLSI, PROCEEDINGS | 1999年

关键词：

D O I：

10.1109/GLSV.1999.757422

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A low power CMOS clock buffer based on charge recycling technique is presented. To accomplish the charge recycling process and avoid introducing the extra short circuit current during the recycling phase, an extra switching circuit and control signal are utilized to keep inverters momentarily tri-state. The feasibility of this design and its improved power efficiency are demonstrated by simulations.

引用

页码：238 / 239

页数：2