Testability issues of system-on-chip design

The paper describes current trends in standardisation of design-for-testability approaches for complex circuits with embedded cores also referred to as system-on-chip. The concept of core wrapper and the corresponding core test language, the main two issues of the forthcoming IEEE P1500 Standard, are briefly introduced. Possible strategies for test integration of cores conforming to the standard are discussed. References to the available IEEE P1500 Standard documents and papers are given, The goal of the paper was to enlighten the issues that may be of most interest to a potential user/designer in the applications of our national electronic industry.