Substrate bias effects in vertical SiGeHBTs fabricated on CMOS-compatible thin film SOI

被引：13

作者：

Chen, TB ^{[1
]}

Bellini, M ^{[1
]}

Zhao, EH ^{[1
]}

Comeau, JP ^{[1
]}

Sutton, AK ^{[1
]}

Grens, CM ^{[1
]}

Cressler, JD ^{[1
]}

Cai, J ^{[1
]}

Ning, TH ^{[1
]}

机构：

[1] Georgia Inst Technol, Sch Elect & Comp Engn, Atlanta, GA 30332 USA

来源：

PROCEEDINGS OF THE 2005 BIPOLAR/BICMOS CIRCUITS AND TECHNOLOGY MEETING | 2005年

关键词：

D O I：

10.1109/BIPOL.2005.1555245

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A comprehensive investigation of substrate bias effects on device performance, thermal properties, and reliability of vertical SiGe HBTs fabricated on CMOS-compatible, thin-film Sol, is presented for the first time. Calibrated 2-D MEDICI simulations are used to support our explanations, and the resultant device design trade-offs encountered in building SiGe HBTs on thin-film SOI are quantitatively assessed.

引用

页码：256 / 259

页数：4

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