Physical Design Aware Selection of Energy-Efficient and Low-Energy Nanometer Flip-Flops

被引：1

作者：

Alioto, Massimo ^{[1
,2
]}

Consoli, Elio ^{[3
]}

Palumbo, Gaetano ^{[3
]}

机构：

[1] Univ Calif Berkeley, BWRC, Berkeley, CA 94720 USA

[2] Univ Siena, Dept Informat Engn, I-53100 Siena, Italy

[3] Catania Univ, Dept Elect Elect & Syst Engn, Catania, Italy

来源：

2010 INTERNATIONAL CONFERENCE ON MICROELECTRONICS | 2010年

关键词：

Energy-Efficiency; Low-Power; Flip-Flops; Clocking; VLSI; Interconnects; Energy-Delay; Layout Impact;

D O I：

10.1109/ICM.2010.5696206

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, a comparison of the most representative flip-flop (FF) topologies in a 65-nm CMOS technology is carried out. For the first time in the literature, local wires capacitances are included in the transistor-level design loop, allowing to reach the actual optimum designs, given the huge impact that local interconnects have on both energy and delay (E-D) ofFFs. The investigation permits to identify the most suitable FFs for low-energy and energy-efficient circuits in nanometer technologies.

引用

页码：60 / 63

页数：4