Current sensing differential logic (CSDL) for low-power and high-speed systems

被引：0

作者：

Park, J ^{[1
]}

Lee, J ^{[1
]}

Kim, W ^{[1
]}

机构：

[1] Seoul Natl Univ, Integrated Syst Lab, Kwanak Gu, Seoul 151742, South Korea

来源：

ISCAS '98 - PROCEEDINGS OF THE 1998 INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-6 | 1998年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

A new low-power high-speed glitch-free logic concept, Current Sensing Differential Logic (CSDL), will be presented. This concept is developed for complex integrated systems of prime importance where the reliability in operation and design flexibility. These performance improvements of power and speed is enabled by restricting the internal voltage swings in the logic evaluation tree. Using the CSDL logic, a 64-bit carry lookahead adder is designed in a 0.6 mu m CMOS technology. The results of the post-layout simulation show that it achieves 2.9ns delay with the power consumption of 21mW at 50MHz with clock buffer.

引用

页码：A129 / A132

页数：4