Low-Power Low-Error Fixed-Width Multiplier Design for Digital Signal Processing

Since a fixed-width multiplier only produces an N-bit output with two N-bit inputs, it is necessary to apply compensation for the truncation error reduction. Previous error compensation circuits often lead to large power consumption. In this paper, we propose a small and accurate fixed-width multiplier design based on two's complement number system. In our approach, the error compensation is modeled as carry inputs to adders in the least significant bit. Consequently, the area and power overheads are small. Compared with previous works, experimental data consistently show that the proposed approach can achieve smaller area and power with a high accuracy.