ROLE OF INTERFACE LAYER IN STRESS-INDUCED LEAKAGE CURRENT IN HIGH-K/METAL-GATE DIELECTRIC STACKS

被引：11
|
作者：
Chang, W. L. [1 ]
Stathis, J. H. [2 ]
Cartier, E. [2 ]
机构：
[1] IBM Microelect, Hopewell Jct, NY 12533 USA
[2] IBM Corp, Div Res, TJ Watson Res Ctr, Yorktown Hts, NY 10598 USA
来源：
2010 INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM | 2010年
关键词：
component; high-k dielectrics; SILC; TDDB;
D O I：
10.1109/IRPS.2010.5488732
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The impact of the Silica-based interface layer (IL) thickness on stress induced leakage current (SILC) on high-k/metal-gate transistors is studied at various constant voltage stresses (CVS) and at various temperatures. It is shown that high-k/metal-gate transistors reliability can be greatly improved with interface layer optimization.
引用
收藏
页码：787 / 791
页数：5
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