共 25 条
- [1] Rigorous Electrical Modeling of Through Silicon Vias (TSVs) with MOS Capacitance Effects [J]. IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2011, 1 (06): : 893 - 903
- [2] Advanced Metallization for 3D Integration [J]. EPTC: 2008 10TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE, VOLS 1-3, 2008, : 212 - 218
- [3] Biancun Xie, 2012, 2012 IEEE 16th Workshop on Signal and Power Integrity, P43, DOI 10.1109/SaPIW.2012.6222908
- [4] Burden R., 2011, Numerical Analysis