A Low-Voltage Measurement Testbed for Metrological Characterization of Algorithms for Phasor Measurement Units

In the recent years, the scientific community is paying great attention to the development of phasor measurement units (PMU) and, particularly, to novel digital signal processing algorithms for these instruments. While the performance of estimation algorithms is usually evaluated through simulations on a PC, the overall PMU accuracy depends on measurement hardware as well (e.g., transducers, data converters, and synchro-nization circuitry). However, the relationship between estimation algorithms accuracy and metrological characteristics of hardware equipment is very difficult to predict or to simulate. Therefore, the performance of different algorithms can be hardly compared when they are actually implemented in real instruments and used in the field. This paper attempts to address this problem by presenting an open testbed for PMU estimation algorithms. The key distinctive feature of the testbed is its ability to evaluate and to compare algorithm accuracy under experimental conditions that include not only the disturbances specified in the IEEE Standard C37.118.1-2011 and its Amendment IEEE C37.118.1a-2014, but also the effects of given uncertainty contributions due to different hardware components. A thorough metrological characterization of the testbed, properly supported by a noise propagation model, is performed in order to quantify such uncertainty contributions and their impact on the estimates of synchrophasor magnitude, phase, fundamental frequency, and rate of change of frequency returned by different algorithms under test. As a case study, three state-of-the-art estimation algorithms are tested in a variety of conditions.