An efficient reduced-order interconnect macromodel for time-domain simulation

被引：0

作者：

Palenius, T ^{[1
]}

Roos, J ^{[1
]}

机构：

[1] Helsinki Univ Technol, Dept Elect & Commun Engn, Circuit Theory Lab, FIN-02015 Helsinki, Finland

来源：

PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL IV: DIGITAL SIGNAL PROCESSING-COMPUTER AIDED NETWORK DESIGN-ADVANCED TECHNOLOGY | 2003年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

As signal speeds grow and feature sizes shrink in digital VLSI circuits, there is an increasing need to correctly model the interconnects between transistors. Since the size of the resulting RLC-interconnect network can be huge, model-reduction algorithms have been developed for replacing the RLC networks with reduced-order frequency-domain models. In this paper, we present an efficient method for interfacing these frequency-domain representations with the time-domain simulation of the original nonlinear circuit.

引用

页码：628 / 631

页数：4

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