An FPGA-based processing pipeline for high-definition stereo video

被引：40

作者：

Greisen, Pierre ^{[1
,2
]}

Heinzle, Simon ^{[2
]}

Gross, Markus ^{[1
,2
]}

Burg, Andreas P. ^{[3
]}

机构：

[1] ETH, CH-8092 Zurich, Switzerland

[2] Disney Res Zurich, Zurich, Switzerland

[3] Ecole Polytech Fed Lausanne, CH-1015 Lausanne, Switzerland

来源：

EURASIP JOURNAL ON IMAGE AND VIDEO PROCESSING | 2011年

关键词：

Video processing pipeline; Stereoscopic video; FPGA; Disparity estimation; Image warping; RECTIFICATION;

D O I：

10.1186/1687-5281-2011-18

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a real-time processing platform for high-definition stereo video. The system is capable to process stereo video streams at resolutions up to 1, 920 x 1, 080 at 30 frames per second (1080p30). In the hybrid FPGA-GPU-CPU system, a high-density FPGA is used not only to perform the low-level image processing tasks such as color interpolation and cross-image color correction, but also to carry out radial undistortion, image rectification, and disparity estimation. We show how the corresponding algorithms can be implemented very efficiently in programmable hardware, relieving the GPU from the burden of these tasks. Our FPGA implementation results are compared with corresponding GPU implementations and with other implementations reported in the literature.

引用

页数：13

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