A 12 GHz All-Digital PLL with linearized chirps for FMCW Radar

被引：0

作者：

Markus, Kempf ^{[1
]}

Juergen, Roeber ^{[1
]}

Frank, Ohnhaeuser ^{[2
]}

Robert, Weigel ^{[3
]}

机构：

[1] Eesy Ic GmbH, Analog Design, Erlangen, Germany

[2] Eesy Ic GmbH, CTO, Erlangen, Germany

[3] Univ Erlangen Nurnberg, Inst Tech Elect, Erlangen, Germany

来源：

2019 26TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS) | 2019年

关键词：

Frequency Synthesis; All-Digital Phase Locked Loops; FMCW Radar; Chirp Linearization;

D O I：

10.1109/icecs46596.2019.8965077

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An accumulator based all-digital PLL for linear FMCW chirp generation is proposed. Operating at a Reference Frequency of 128MHz the Phase Noise at 100 kHz offset measures -80 dBc/Hz. The proposed chirp linearization scheme allows for a wide range of chirp periods from 40 us up to 200 ms with an RMS Frequency Error of down to 7.26 kHz for slow and 882 kHz for fast chirps. Without dithering, the digitally, switched capacitor controlled oscillator presented in this work achieves an average step size of below 25 kHz while ranging from 11.596 GHz to 12.783 GHz.

引用

页码：482 / 485

页数：4

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