A Novel Sub-Cycle-Based Method for Estimation of Decaying DC Component and Fundamental Phasor

被引:11
作者
Kumar, Bandi Ravi [1 ]
Mohapatra, Abheejeet [1 ]
Chakrabarti, Saikat [1 ]
机构
[1] Indian Inst Technol Kanpur, Dept Elect Engn, Kanpur 208016, Uttar Pradesh, India
关键词
Decaying dc component (DDC); half-cycle discrete Fourier transform (HCDFT); high-speed relaying; phasor estimation; phasor measurement unit; power system protection; OFFSET; REMOVAL; ALGORITHM;
D O I
10.1109/TIM.2021.3122199
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Accurate estimation of the fundamental phasors of voltage or current is a challenge to power system engineers. It becomes even more challenging when the decaying dc component (DDC) is present in the signal. This article proposes a sub- cycle-based algorithm for reducing the effect of DDC for accurate estimation of the phasor of fault current signal in the presence of odd harmonics and multiple DDCs. In the proposed algorithm, the equality property of the sinusoidal signal samples around its peak is utilized to estimate DDC with only four samples and the window length requirement of half-cycle plus two samples. A novel noise removal methodology is also proposed. The fundamental phasor is calculated by taking the difference of the half-cycle discrete Fourier transform (HCDFT) of fault current and HCDFT of DDC. Simulations are performed to show the effectiveness of the proposed method, and it is compared with few previous estimation algorithms. Tests with the system-generated signals show the efficacy and accuracy of the proposed sub-cyclebased method.
引用
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页数:10
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