Configurable multi-rate decoder architecture for QC-LDPC codes based broadband broadcasting system

被引：14

作者：

Zhang, Luoming ^{[1
]}

Gui, Lin ^{[2
]}

Xu, Youyun ^{[2
]}

Zhang, Wenjun ^{[1
]}

机构：

[1] SJTU, Inst Image Commun & Informat Proc, Dept Elect Engn, Shanghai 200240, Peoples R China

[2] SJTU, Inst Wireless Commun Technol, Dept Elect Engn, Shanghai 200240, Peoples R China

来源：

IEEE TRANSACTIONS ON BROADCASTING | 2008年 / 54卷 / 02期

基金：

中国国家自然科学基金;

关键词：

base-matrix; broadcast; channel coding; FPGA; MMSA; multi-rate; quasi-cyclic low-density parity-check codes (QC-LDPCC); scalable throughput;

D O I：

10.1109/TBC.2007.913400

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper we present a Base-matrix based decoder architecture for multi-rate QC-LDPC codes proposed in broadband broadcasting system. We use the Modified Min-Sum Algorithm (MMSA) as the decoding algorithm in this architecture, which lowers the complexity of the LDPC decoder while keeping almost the same performance or even better. Based on this algorithm, we designed a novel check node processing unit to reduce the complexity of the decoder and facilitate the multiplex of the processing units. The decoder designed with hardware constraints is not only scalable in throughput, but also easily configurable to support different QC-LDPC codes flexible in code rate and code length.

引用

页码：226 / 235

页数：10

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