Exploratory study on power-efficient silicon nano-wire dynamic NMOSFET/PMESFET logic

被引：2

作者：

Bindal, A. ^{[1
]}

Hamedi-Hagh, S. ^{[2
]}

机构：

[1] San Jose State Univ, Dept Comp Engn, San Jose, CA 95192 USA

[2] San Jose State Univ, Dept Elect Engn, San Jose, CA 95192 USA

来源：

IET SCIENCE MEASUREMENT & TECHNOLOGY | 2007年 / 1卷 / 02期

关键词：

D O I：

10.1049/iet-smt:20060057

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The latest techniques in fabricating silicon-based, vertical surrounding gate MOSFETs (SGFET) instigate the pathway towards building the next generation ultra large-scale integration (ULSI). The study shows the design and optimisation of surrounding gate n-channel MOSFETs and p-channel MESFETs used in dynamic differential domino circuits suitable for an area-efficient technology. Three-dimensional device simulations investigate the maximum device transconductance and minimum OFF current of vertical, metal-gated nano-wire NMOSFETs and PMESFETs as a function of wire radius and doping concentration. Two-dimensional process simulations are carried out on the optimum transistor designs, and non-ideal device characteristics are measured. A family of differential dynamic circuits composed of a two-input AND ( OR), and two-input XOR gates and a full adder are built to measure worst-case pre-charge and evaluate function delays, power dissipation and layout area.

引用

页码：121 / 130

页数：10

共 26 条

[1] Analysis and comparison on full adder block in submicron technology [J].

Alioto, M ;

Palumbo, G .

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2002, 10 (06) :806-823

[2] FABRICATION OF EXTREMELY THIN SILICON-ON-INSULATOR FOR FULLY-DEPLETED CMOS APPLICATIONS [J].

BINDAL, A ;

ROVEDO, N ;

RESTIVO, J ;

GALLI, C ;

OGURA, S .

THIN SOLID FILMS, 1993, 232 (01) :105-109

[3] A review of 0.18-μm full adder performances for tree structured arithmetic circuits [J].

Chang, CH ;

Gu, JM ;

Zhang, MY .

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2005, 13 (06) :686-695

[4] Silicon nanowire devices [J].

Chung, SW ;

Yu, JY ;

Heath, JR .

APPLIED PHYSICS LETTERS, 2000, 76 (15) :2068-2070

[5] High performance silicon nanowire field effect transistors [J].

Cui, Y ;

Zhong, ZH ;

Wang, DL ;

Wang, WU ;

Lieber, CM .

NANO LETTERS, 2003, 3 (02) :149-152

[6] The design of DNA self-assembled computing circuitry [J].

Dwyer, C ;

Vicci, L ;

Poulton, J ;

Erie, D ;

Superfine, R ;

Washburn, S ;

Taylor, RM .

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2004, 12 (11) :1214-1220

[7] Performance simulation of nanoscale silicon rod field-effect transistor logic [J].

Dwyer, C ;

Vicci, L ;

Taylor, RM .

IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2003, 2 (02) :69-74

[8]

ECOFFEY S, 2005, IEEE INT SOL STAT CI, P260

[9] Ultrahigh-density silicon nanobridges formed between two vertical silicon surfaces [J].

Islam, MS ;

Sharma, S ;

Kamins, TI ;

Williams, RS .

NANOTECHNOLOGY, 2004, 15 (05) :L5-L8

[10] Ti-catalyzed Si nanowires by chemical vapor deposition: Microscopy and growth mechanisms [J].

Kamins, TI ;

Williams, RS ;

Basile, DP ;

Hesjedal, T ;

Harris, JS .

JOURNAL OF APPLIED PHYSICS, 2001, 89 (02) :1008-1016

← 1 2 3 →