Dielectric integrity test for flip-chip devices with Cu/low-k interconnects

Migration to low-k dielectric materials in wafer-fab back-end-of-line (BEOL) interconnect schemes is necessary for improved electrical performance of smaller and tighter geometries enabled by advanced silicon technology nodes. Unfortunately, low-k dielectrics are mechanically weaker compared to previous generation materials. Concurrent technology and market driven changes such as tighter bump pitch and replacing StiPb with Pb-free solder bump composition are leading to increased stress and risk to damage of the inherently weaker dielectrics in flip-chip packages. It is, hence, critical to characterize the structural integrity of the BEOL interconnect schemes containing low-k dielectrics. Traditional environmental reliability stress testing, while effective, is time-consuming and expensive, and not conducive for fast learning cycles required during early development phases. This paper demonstrates the utility of a test that enables rapid and accurate assessment of the mechanical integrity of low-K dielectrics. Silicon dies with Cu/low-k interconnect are assembled on to an organic substrate through flip-chip bumps, and cooled. The mismatch in coefficient of thermal expansion (CTE) between the silicon die and organic substrate can induce failure if the resulting thermal residual stress exceeds the strength of the structure. Since the level of thermal residual stress depends on the temperature, the magnitude of induced stress can be controlled by subjecting the sample to various degrees of cooling. Consequently, the strength of the BEOL structures can be determined, in conjunction with thermo-mechanical stress analyses results from finite element simulation of the test.