3D wafer level packaging

被引：0
|
作者：
Savastiouk, S [1 ]
Siniaguine, O [1 ]
Korczynski, E [1 ]
Tilenschi, M [1 ]
机构：
[1] Tru Si Technol, Mkt, Sunnyvale, CA 94086 USA
来源：
MICRO MATERIALS, PROCEEDINGS | 2000年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：240 / 243
页数：4
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