On thermal stresses and reliability of a PBGA chip scale package

被引:0
|
作者
Hong, BZ [1 ]
Su, LS [1 ]
机构
[1] IBM Corp, Microelect Div, Hopewell Jct, NY 12533 USA
来源
48TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE - 1998 PROCEEDINGS | 1998年
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Thermomechanical analysis using the nonlinear finite element method was performed to study the thermal stresses and reliability problems of a flip chip plastic ball grid array (PBGA) chip scale package (CSP). The package under investigation has the fully populated PBGA solder joints in an array pitch of 1.27mm. A cyclic temperature load of 0-100 degrees C at a frequency of 2 cycles per hour was applied to the modeled package. The dependence of solder joint reliability on the CSP configuration and the use of mold compound was demonstrated for various chip sizes varying from 5mm to 20mm. The analysis results show that the chip-outline solder joint may fail earlier than any other solder joint in the modeled package. This confirms both experimental and modeling observations in literature that the interior PBGA solder joint does fail mainly caused by the thermally induced warpage of organic-based package. It is contrary to the classical DNP theory used in predicting the fatigue failure location and mechanism of solder joints in the ceramic-based packages. The overmold flip chip PBGA chip scale package has a mean thermal fatigue life of the first failed solder joint that is approximately 1.2X that of the standard flip chip PBGA scale package without overmold.
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收藏
页码:503 / 510
页数:8
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