Operational voltage reduction of flash memory using high-κ composite tunnel barriers

被引：13

作者：

Verma, Sarves ^{[1
]}

Pop, Eric ^{[2
,3
]}

Kapur, Pawan

Parat, Krishna ^{[2
,4
]}

Saraswat, Krishna C. ^{[4
]}

机构：

[1] Stanford Univ, Dept Mat Sci & Engn, Ctr Integrated Syst, Stanford, CA 94305 USA

[2] Intel Corp, Santa Clara, CA 95054 USA

[3] Univ Illinois, Dept Elect & Comp Engn, Urbana, IL 61801 USA

[4] Stanford Univ, Dept Elect & Elect Engn, Ctr Integrated Syst, Stanford, CA 94305 USA

来源：

IEEE ELECTRON DEVICE LETTERS | 2008年 / 29卷 / 03期

关键词：

flash memory; flash operating constraints; high-kappa dielectrics; program disturb; read disturb; retention; tunnel barrier engineering;

D O I：

10.1109/LED.2007.915376

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We explore the performance of symmetric (low-kappa/high-kappa/low-kappa) and asymmetric (low-kappa/high-kappa) composite tunnel barriers with conventional Flash constraints of retention, erase, read and program disturbs. Simulations, including five different high-kappa materials, were performed under these criteria to minimize the programming voltage V-prog. Among all constraints, we find read disturb to be the most restrictive both in terms of lowering V-prog and choosing the high-kappa materials for such stacks. Furthermore, the symmetric barrier stack is found to be more promising versus the asymmetric barrier stack. For the common read disturb voltages of 2.5 and 3.6 V, the lowest V-prog of similar to 4 and 5 V, respectively (relative to the floating gate), are obtained. In addition, the maximum required operating Flash voltage is found to be 30% - 40% lower than the prevalent voltages.

引用

页码：252 / 254

页数：3