Operational voltage reduction of flash memory using high-κ composite tunnel barriers

被引:13
作者
Verma, Sarves [1 ]
Pop, Eric [2 ,3 ]
Kapur, Pawan
Parat, Krishna [2 ,4 ]
Saraswat, Krishna C. [4 ]
机构
[1] Stanford Univ, Dept Mat Sci & Engn, Ctr Integrated Syst, Stanford, CA 94305 USA
[2] Intel Corp, Santa Clara, CA 95054 USA
[3] Univ Illinois, Dept Elect & Comp Engn, Urbana, IL 61801 USA
[4] Stanford Univ, Dept Elect & Elect Engn, Ctr Integrated Syst, Stanford, CA 94305 USA
关键词
flash memory; flash operating constraints; high-kappa dielectrics; program disturb; read disturb; retention; tunnel barrier engineering;
D O I
10.1109/LED.2007.915376
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We explore the performance of symmetric (low-kappa/high-kappa/low-kappa) and asymmetric (low-kappa/high-kappa) composite tunnel barriers with conventional Flash constraints of retention, erase, read and program disturbs. Simulations, including five different high-kappa materials, were performed under these criteria to minimize the programming voltage V-prog. Among all constraints, we find read disturb to be the most restrictive both in terms of lowering V-prog and choosing the high-kappa materials for such stacks. Furthermore, the symmetric barrier stack is found to be more promising versus the asymmetric barrier stack. For the common read disturb voltages of 2.5 and 3.6 V, the lowest V-prog of similar to 4 and 5 V, respectively (relative to the floating gate), are obtained. In addition, the maximum required operating Flash voltage is found to be 30% - 40% lower than the prevalent voltages.
引用
收藏
页码:252 / 254
页数:3
相关论文
共 39 条
[31]   Low-voltage and low-current flash memory using source induced band-to-band tunneling hot electron injection to perform programming [J].
Pan, LY ;
Zhu, J ;
Zeng, Y ;
Fu, YX ;
Wu, D ;
Duan, ZG ;
Liu, JZ ;
Sun, L .
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 2003, 42 (4B) :2028-2032
[32]   Low-voltage and low-current flash memory using source induced band-to-band tunneling hot electron injection to perform programming [J].
Pan, Liyang ;
Zhu, Jun ;
Zeng, Ying ;
Fu, Yuxia ;
Wu, Dong ;
Duan, Zhigang ;
Liu, Jianzhao ;
Sun, Lei .
Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, 2003, 42 (4 B) :2028-2032
[33]   High-Endurance Ferroelectric NOR Flash Memory Using (Ca,Sr)Bi2Ta2O9 FeFETs [J].
Takahashi, Mitsue ;
Zhang, Wei ;
Sakai, Shigeki .
2018 IEEE 10TH INTERNATIONAL MEMORY WORKSHOP (IMW), 2018, :58-61
[34]   Investigation of Band-Gap Engineered Silicon-Oxide-Nitride-Oxide-Silicon Flash Memory with High-k Dielectrics in Tunnel Barrier and Its Impact on Charge Retention Dynamics [J].
Jain, Sonal ;
Neema, Vaibhav ;
Gupta, Deepika ;
Vishvakarma, Santosh Kumar .
JOURNAL OF NANOELECTRONICS AND OPTOELECTRONICS, 2016, 11 (06) :663-668
[35]   Performance Enhancement for Charge Trapping Memory by Using Al2O3/HfO2/Al2O3 Tri-Layer High-κ Dielectrics and High Work Function Metal Gate [J].
Hou, Zhaozhao ;
Wu, Zhenhua ;
Yin, Huaxiang .
ECS JOURNAL OF SOLID STATE SCIENCE AND TECHNOLOGY, 2018, 7 (06) :N91-N95
[36]   A novel high-κ SONOS memory using TaN/Al2O3/Ta2O5/HfO2/Si structure for fast speed and long retention [J].
Wang, X ;
Kwong, DL .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2006, 53 (01) :78-82
[37]   SONOS-type flash memory cell with metal/Al2O3/SiN/Si3N4/Si structure for low-voltage high-speed program/erase operation [J].
Shim, Sun Il ;
Yeh, Frank C. ;
Wang, X. W. ;
Ma, T. P. .
IEEE ELECTRON DEVICE LETTERS, 2008, 29 (05) :512-514
[38]   Incorporation effect of thin Al2O3 layers on ZrO2-Al2O3 nanolaminates in a composite oxide-high-κ-oxide stack for floating-gate flash memory devices [J].
Joo, Moon Sig ;
Lee, Seung Ryong ;
Yang, Hong-Seon ;
Hong, Kwon ;
Jang, Se-Aug ;
Koo, Jaehyoung ;
Kim, Jaemun ;
Shin, Seungwoo ;
Kim, Myungok ;
Pyi, Seungho ;
Kwak, Nojung ;
Kim, Jin Woong .
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2007, 46 (4B) :2193-2196
[39]   New Three-Dimensional High-Density Stacked-Surrounding Gate Transistor (S-SGT) flash memory architecture using self-aligned interconnection fabrication technology without photolithography process for tera-bits and beyond [J].
Sakuraba, H ;
Kinoshita, K ;
Tanigami, T ;
Yokoyama, T ;
Horii, S ;
Saitoh, M ;
Sakiyama, K ;
Endoh, T ;
Masuoka, F .
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2004, 43 (4B) :2217-2219