Heterogeneity-aware Multicore Synchronization for Intermittent Systems

被引:9
|
作者
Chen, Wei-Ming [1 ,2 ]
Kuo, Tei-Wei [2 ,3 ]
Hsiu, Pi-Cheng [1 ,2 ,4 ]
机构
[1] Acad Sinica, Res Ctr Informat Technol Innovat CITI, Taipei, Taiwan
[2] Natl Taiwan Univ, Dept Comp Sci & Informat Engn, Taipei, Taiwan
[3] City Univ Hong Kong, Dept Comp Sci, Hong Kong, Peoples R China
[4] Natl Taiwan Univ, Coll Elect Engn & Comp Sci, Taipei, Taiwan
关键词
Multicore synchronization; task concurrency; data consistency; batteryless devices; intermittent computing; MODEL;
D O I
10.1145/3476992
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Intermittent systems enable batteryless devices to operate through energy harvesting by leveraging the complementary characteristics of volatile (VM) and non-volatile memory (NVM). Unfortunately, alternate and frequent accesses to heterogeneous memories for accumulative execution across power cycles can significantly hinder computation progress. The progress impediment is mainly due to more CPU time being wasted for slow NVM accesses than for fast VM accesses. This paper explores how to leverage heterogeneous cores to mitigate the progress impediment caused by heterogeneous memories. In particular, a delegable and adaptive synchronization protocol is proposed to allow memory accesses to be delegated between cores and to dynamically adapt to diverse memory access latency. Moreover, our design guarantees task serializability across multiple cores and maintains data consistency despite frequent power failures. We integrated our design into FreeRTOS running on a Cypress device featuring heterogeneous dual cores and hybrid memories. Experimental results show that, compared to recent approaches that assume single-core intermittent systems, our design can improve computation progress at least 1.8x and even up to 33.9x by leveraging core heterogeneity.
引用
收藏
页数:22
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