The Test Pattern Generation for Digital Integrated Circuits Based on CA-IA-PSO Algorithm

被引：2

作者：

Zhang Jiali ^{[1
]}

Zhang Lin ^{[1
]}

Yang Yun ^{[1
]}

Niu Tianlin ^{[1
]}

Zhang Long ^{[1
]}

Xu XiaoDong ^{[1
]}

机构：

[1] Air Force Engn Univ, Air & Missile Def Coll, Xian 710051, Shaanxi, Peoples R China

来源：

2015 SEVENTH INTERNATIONAL CONFERENCE ON MEASURING TECHNOLOGY AND MECHATRONICS AUTOMATION (ICMTMA 2015) | 2015年

关键词：

Digital integrated circuits; test pattern generation; test vector; IA-PSO algorithm; CA algorithm;

D O I：

10.1109/ICMTMA.2015.322

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In order to improve the ability to get rid of partial extreme spot and the diversity of population in evolution, the immunity mechanism of IA algorithm is imported into PSO algorithm to form IA-PSO algorithm. For the purpose of raising fault rate and shortening test pattern generation time, CA algorithm is imported into IA-PSO algorithm to form CA-IA- PSO algorithm. Finally, adopting single stuck-at fault and using different algorithms to the simulation experiment of test pattern generation for digital integrated circuits, the result of the experiment is that CA-IA-PSO algorithm can solve the problem of test pattern generation more practically and efficiently, especially the bigger digital integrated circuits.

引用

页码：1316 / 1320

页数：5

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Jinno C., 2003, Transactions of the Institute of Electronics, Information and Communication Engineers D-I, VJ86D-I, P682

[4]

Yang Shiyuan, 2000, FAULTS DIAGNOSIS MEA, P39

[5]

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