A new compact architecture for AES with optimized ShiftRows operation

In this paper we present a new compact iterative architecture of 32-bit datapath for the AES block cipher. We propose a new way of implementing ShiftRows and InvShiftRows operation, which is realized by the simple enable function of registers and five 2-to-1 multiplexors of eight bits length. A new compact key generation unit of 32-bit datapath is also proposed to generate round keys on-the-fly for both encryption and decryption. The hardware resource is maximally shared for encryption and decryption. The implementation requires 9843 gate equivalents and provides a throughput of 247 Mbit/s on the CSMC's 0.35 mu m CMOS technology. The comparison with the best previous work shows that it has better throughput and area performance parameters.