CMOS Transistor Scaling Past 32nm and Implications on Variation

被引：32
作者：
Kuhn, Kelin J. [1 ]
机构：
[1] Intel Corp, Portland Technol Dev, Hillsboro, OR 97124 USA
来源：
2010 IEEE/SEMI ADVANCED SEMICONDUCTOR MANUFACTURING CONFERENCE | 2010年
关键词：
THRESHOLD VOLTAGE FLUCTUATION; METAL-GATE TRANSISTORS; DECANANOMETER MOSFETS; LOGIC TECHNOLOGY; SILICON; VARIABILITY; THICKNESS; DESIGN; DEVICE; DELTA;
D O I：
10.1109/ASMC.2010.5551461
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper explores CMOS transistor scaling past the 32nm generation and its implications on variation. Front-end variation sources are reviewed, with detailed discussion on lithography and polish variation sources past 32nm. New transistor architectures are discussed, with emphasis on benefits and challenges relative to variation. Detailed variation measurement techniques are reviewed, with supporting multi-generational trend results, including data from the 32nm node.
引用
收藏
页码：241 / 246
页数：6
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