Dual gate synthetic MoS2 MOSFETs with 4.56μF/cm2 channel capacitance, 320μS/μm Gm and 420 μA/μm Id at 1V Vd/100nm Lg

被引：3

作者：

Wu, Xiangyu ^{[1
]}

Cott, Daire ^{[1
]}

Lin, Zaoyang ^{[1
]}

Shi, Yuanyuan ^{[1
]}

Groven, Benjamin ^{[1
]}

Morin, Pierre ^{[1
]}

Verreck, Devin ^{[1
]}

Smets, Quentin ^{[1
]}

Medina, Henry ^{[1
]}

Sutar, Surajit ^{[1
]}

Asselberghs, Inge ^{[1
]}

Radu, Iuliana ^{[1
]}

Lin, Dennis ^{[1
]}

机构：

[1] IMEC, Leuven, Belgium

来源：

2021 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2021年

关键词：

D O I：

10.1109/IEDM19574.2021.9720695

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We have engineered dual gate (DG) MoS2 transistors with scaled top and back gate stacks based on a surface physisoiption ALD approach. A GdAlOx. interfacial layer (IL) between the TMA 'soak' seed and the HfO2 layer has been introduced to improve Vt control, hysteresis, and long channel mobility. Connected dual gate MOSFET with 1-2ML MoS2 channel reaches 420 mu A/um drain current and 4.56 mu F/cm(2) capacitance at 2.6V gate bias (similar to 5x10(13)/cm(2) sheet charge density).

引用

页数：4

共 2 条

[1] Dual gate synthetic WS2 MOSFETs with 120μS/μm Gm 2.7μF/cm2 capacitance and ambipolar channel
Lin, Dennis
Wu, Xiangyu
Cott, Daire
Verreck, Devin
Groven, Benjamin
Sergeant, Stephanie
Smets, Quentin
Sutar, Surajit
Asselberghs, Inge
Radu, Iuliana
2020 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2020,
[2] First Demonstration of GAA Monolayer-MoS2 Nanosheet nFET with 410 μA/μm ID at 1V VD at 40nm gate length
Chung, Yun-Yan
Chou, Bo-Jhih
Hsu, Chen-Feng
Yun, Wei-Sheng
Li, Ming-Yang
Su, Sheng-Kai
Liao, Yu-Tsung
Lee, Meng-Chien
Huang, Guo-Wei
Liew, San-Lin
Shen, Yun-Yang
Chang, Wen-Hao
Chen, Chien-Wei
Kei, Chi-Chung
Wang, Han
Wong, H. -S. Philip
Lee, T. Y.
Chien, Chao-Hsin
Cheng, Chao-Ching
Radu, Iuliana P.
2022 INTERNATIONAL ELECTRON DEVICES MEETING, IEDM, 2022,

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