Accelerating a MPEG-4 video decoder through custom software/hardware co-design

被引:0
|
作者
Diaz, Jorge L. [1 ]
Barreto, Dacil [1 ]
Garcia, Luz [1 ]
Marrero, Gustavo [1 ]
Carballo, Pedro P. [1 ]
Nunez, Antonio [1 ]
机构
[1] Univ Las Palmas Gran Canaria, IUMA, Inst Appl Microelect, Las Palmas Gran Canaria 35017, Spain
来源
VLSI CIRCUITS AND SYSTEMS III | 2007年 / 6590卷
关键词
MPEG-4 video decoder; CASSE; motion compensation; IDCT; software/hardware co-design; hardware coprocessors; verification; integration; FPGA;
D O I
10.1117/12.722068
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper we present a novel methodology to accelerate an MPEG-4 video decoder using software/hardware co-design for wireless DAB/DMB networks. Software support includes the services provided by the embedded kernel mu C/OS-II, and the application tasks mapped to software. Hardware support includes several custom co-processors and a communication architecture with bridges to the main system bus and with a dual port SRAM. Synchronization among tasks is achieved at two levels, by a hardware protocol and by kernel level scheduling services. Our reference application is an MPEG-4 video decoder composed of several software functions and written using a special C++ library named CASSE. Profiling and space exploration techniques were used previously over the Advanced Simple Profile (ASP) MPEG-4 decoder to determinate the best HW/SW partition developed here. This research is part of the ARTEMI project and its main goal is the establishment of methodologies for the design of real-time complex digital systems using Programmable Logic Devices with embedded microprocessors as target technology and the design of multimedia systems for broadcasting networks as reference application.
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页数:8
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