A Distributed Oscillator Based All-Digital PLL With a 32-Phase Embedded Phase-to-Digital Converter

被引：18

作者：

Takinami, Koji ^{[1
]}

Strandberg, Richard ^{[1
]}

Liang, Paul C. P. ^{[1
]}

de Mercey, Gregoire Le Grand ^{[1
]}

Wong, Tony

Hassibi, Mahnaz ^{[1
]}

机构：

[1] Panason Wireless Res Lab, Cupertino, CA 95014 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2011年 / 46卷 / 11期

关键词：

Distributed oscillator; rotary traveling wave; all-digital phase-locked loop; digitally-controlled oscillator; time-to-digital converter; phase-to-digital converter; low phase noise; FREQUENCY-SYNTHESIZER; TIME; NOISE;

D O I：

10.1109/JSSC.2011.2164011

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a wide-bandwidth, low-noise 4 GHz All-Digital PLL. It uses a rotary traveling wave oscillator (RTWO) as the oscillator core. By using multiphase signals available from the RTWO, the analog phase information is directly converted into the digital domain. Unlike the conventional time-to-digital converter (TDC) approach, it eliminates power hungry inverter delay chains as well as real time period normalization. The proposed approach significantly simplifies the ADPLL architecture while maintaining excellent phase noise. The PLL is implemented in a 65 nm CMOS process. The 32-phase embedded phase-to-digital converter (PDC) achieves 2 pi/64 phase resolution. The measured in-band phase noise is -108 dBc/Hz at 4 GHz with a 78 MHz reference and a 1 MHz loop bandwidth.

引用

页码：2650 / 2660

页数：11

共 30 条

[1] Phase noise and jitter in CMOS ring oscillators [J].