A model-selection approach to the VLSI design of vector quantizers

A formal methodology supports the design of digital devices for Hierarchical Vector Quantization (HVQ). A model-selection approach based on the Minimum Description Length criterion is enhanced by circuit-related aspects allowing efficient design. The resulting parameters drive the subsequent digital VLSI realization, which yields a HVQ chip providing cost-effective, computationally efficient real-time performances. Real-world applications support the consistency of the VQ approach and the effectiveness of the HVQ device.