Concurrent Error Detection in Bit-Serial Normal Basis Multiplication Over GF(2m) Using Multiple Parity Prediction Schemes

被引：18

作者：

Lee, Chiou-Yng ^{[1
]}

Meher, Pramod Kumar ^{[2
]}

Patra, Jagdish Chandra ^{[3
]}

机构：

[1] Lunghwa Univ Sci & Technol, Dept Comp Informat & Network Engn, Tao Yuan 33306, Taiwan

[2] Inst Infocomm Res, Dept Commun Syst, Singapore 138632, Singapore

[3] Nanyang Technol Univ, Sch Comp Engn, Singapore 639798, Singapore

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2010年 / 18卷 / 08期

基金：

日本学术振兴会;

关键词：

Concurrent error detection (CED); cryptography; normal basis; parity prediction; BASES;

D O I：

10.1109/TVLSI.2009.2020593

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

New bit-serial architectures with concurrent error detection capability are presented to detect erroneous outputs in bit-serial normal basis multipliers over G F (2(m)) using single and multiple-parity prediction schemes. It is shown that different types of normal basis multipliers could be realized by similar architectures. The proposed architectures can detect errors with nearly 100% probability.

引用

页码：1234 / 1238

页数：5

共 14 条

[1]

Agrawal D. P., 1980, Journal of Digital Systems, V4, P337

[2] On concurrent detection of errors in polynomial basis multiplication [J].