A Wide-Range All-Digital Delay-Locked Loop in 65nm CMOS Technology

被引：0
|
作者：
Chung, Ching-Che [1 ]
Chang, Chia-Lin [1 ]
机构：
[1] Natl Chung Cheng Univ, Dept Comp Sci & Informat Engn, Chiayi, Taiwan
来源：
2010 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN AUTOMATION AND TEST (VLSI-DAT) | 2010年
关键词：
All digital delay-locked loop (ADDLL); digital controlled delay line; cycle-controlled delay unit; wide-range operation; DLL;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
An ultra wide-range delay-locked loop (DLL) has been fabricated in 65nm CMOS technology. The proposed leakage delay unit (LDU) can easily generate a large propagation delay to reduce the difficulties to build up the high-speed digital counter in the cycle-controlled delay unit (CCDU) for a very low-frequency operation. The proposed DLL circuit can operate from 500 KHz to 1 GHz, and the power consumption is 1.8mW @1GHz with very small active area (0.01mm(2)).
引用
收藏
页码：66 / 69
页数：4
相关论文
共 50 条
  • [31] A fast-locking all-digital delay-locked loop for phase/delay generation in an FPGA
    陈柱佳
    杨海钢
    刘飞
    王瑜
    半导体学报, 2011, 32 (10) : 139 - 146
  • [32] 100MHz all-digital delay-locked loop for low power application
    Kim, BS
    Kim, LS
    ELECTRONICS LETTERS, 1998, 34 (18) : 1739 - 1740
  • [33] An All-Digital Delay-Locked Loop for High-Speed Memory Interface Applications
    Chen, Shih-Lun
    Ho, Ming-Jing
    Sun, Yu-Ming
    Lin, Maung Wai
    Lai, Jung-Chin
    2014 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), 2014,
  • [34] A mixed-mode delay-locked loop for wide-range operation and multiphase outputs
    Cheng, KH
    Lo, YL
    Yu, WF
    PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II: COMMUNICATIONS-MULTIMEDIA SYSTEMS & APPLICATIONS, 2003, : 196 - 199
  • [35] A wide-range multiphase delay-locked loop using mixed-mode VCDLs
    Yang, RJ
    Liu, SI
    IEICE TRANSACTIONS ON ELECTRONICS, 2005, E88C (06) : 1248 - 1252
  • [36] An all-digital reused-SAR delay-locked loop with adjustable duty cycle
    Lin, Wei-Ming
    Liu, Shen-Luan
    2007 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE, PROCEEDINGS OF TECHNICAL PAPERS, 2007, : 312 - +
  • [37] A 0.1-1.5 GHz All-Digital Phase Inversion Delay-Locked Loop
    Han, Sangwoo
    Kim, Taejin
    Kim, Jongsun
    PROCEEDINGS OF THE 2013 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC), 2013, : 341 - 344
  • [38] AN ULTRA LOW-VOLTAGE/POWER-EFFICIENT ALL-DIGITAL DELAY LOCKED LOOP IN 55 nm CMOS TECHNOLOGY
    Cheng, Chun-Yuan
    Wang, Jinn-Shyan
    Yeh, Cheng-Tai
    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2012, 21 (08)
  • [39] A High-Resolution Wide-Range Dual-Loop Digital Delay-Locked Loop Using a Hybrid Search Algorithm
    Han, Sangwoo
    Kim, Jongsun
    2012 IEEE ASIAN SOLID STATE CIRCUITS CONFERENCE (A-SSCC), 2012, : 293 - 296
  • [40] Wide-range harmonic lock detector with real-time delay measurement of delay-locked loop
    Kim, Sangseob
    Hyoung, Chang-Hee
    Park, Kyoung-Hwan
    ELECTRONICS LETTERS, 2015, 51 (02) : 136 - 137
12345