A Wide-Range All-Digital Delay-Locked Loop in 65nm CMOS Technology

被引：0
|
作者：
Chung, Ching-Che [1 ]
Chang, Chia-Lin [1 ]
机构：
[1] Natl Chung Cheng Univ, Dept Comp Sci & Informat Engn, Chiayi, Taiwan
来源：
2010 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN AUTOMATION AND TEST (VLSI-DAT) | 2010年
关键词：
All digital delay-locked loop (ADDLL); digital controlled delay line; cycle-controlled delay unit; wide-range operation; DLL;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
An ultra wide-range delay-locked loop (DLL) has been fabricated in 65nm CMOS technology. The proposed leakage delay unit (LDU) can easily generate a large propagation delay to reduce the difficulties to build up the high-speed digital counter in the cycle-controlled delay unit (CCDU) for a very low-frequency operation. The proposed DLL circuit can operate from 500 KHz to 1 GHz, and the power consumption is 1.8mW @1GHz with very small active area (0.01mm(2)).
引用
收藏
页码：66 / 69
页数：4
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