All-digital PLL array provides reliable distributed clock for SOCs

被引：0

作者：

Javidan, M. ^{[1
]}

Zianbetov, E. ^{[1
]}

Anceau, F. ^{[1
]}

Galayko, D. ^{[1
]}

Korniienko, A. ^{[2
]}

Colinet, E. ^{[2
]}

Scorletti, G. ^{[3
]}

Akre, J. M. ^{[4
]}

Juillard, J. ^{[4
]}

机构：

[1] UPMC Sorbonne Univ, LIP6 Lab, 4 Pl Jussieu, F-75252 Paris 05, France

[2] CEA LETI, F-38054 Grenoble, France

[3] ECL, AMPERE, F-69134 Ecully, France

[4] Supelec, F-91192 Gif Sur Yvette, France

来源：

2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2011年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This brief addresses the problem of clock generation and distribution in globally synchronous locally synchronous chips. A novel architecture of clock generation based on network of coupled all-digital PLLs is proposed. Solutions are proposed to overcome the issues of stability and undesirable synchronized modes (modelocks) of high-order bidirectional PLL networks. The VLSI implementation of the network is discussed in CMOS65 nm technology and the simulation results prove the reliability of the global synchronization by the proposed method.

引用

页码：2589 / 2592

页数：4

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